The present invention relates to improvements in a mass semiconductor memory having a plurality of cell array blocks, and more particularly to improvements in a mass semiconductor dynamic random access memory (DRAM).
Recently, the DRAMs are remarkably improved in components per chip to such an extent that there are mass-produced DRAMs in which one chip has a 16M-bit memory capacity. In such a high density DRAM, it is required that the voltage read out from a memory cell is maintained at a value not less than a predetermined value, that wiring delay is restrained and that the areas to be simultaneously operated are reduced in number to lower the power consumption. Accordingly, the number of memory cells connected to one bit line or one word line cannot excessively be increased. In this connection, there is used an arrangement in which the cell array on one chip is divided into a plurality of cell array blocks.
A conventional high density DRAM of the type above-mentioned is usually arranged such that one column decoder is disposed for a plurality of cell array blocks, and that column select lines connected to the output terminals of the column decoder are disposed in parallel with bit lines over the cell arrays and extend over the cell array blocks such that each column-select line is shared by the cell array blocks. Further, sub data buses are disposed respectively for each cell array block at right angles to the column select lines, and the column select lines control the connection of the sub data buses to sense amplifiers in the cell array blocks. Generally, the column select lines are formed of the second layer of aluminium and extend in parallel with the bit lines on the cell arrays. Generally, the word lines are formed of the first layer of aluminium. Accordingly, the column select lines are disposed on the word lines. The following description will discuss a conventional DRAM of the type above-mentioned with reference to FIGS. 10, 11, 12.
FIG. 12 is a schematic view illustrating the block diagram of a chip in its entirety. A 16-MDRAM having an arrangement of 1M.times.16 bits is shown by way of example. Each of cell arrays is largely divided into four portions which correspond to data input/output terminals I/O0.about.3, I/O4.about.7, I/O8.about.11, I/O12.about.15. FIG. 11 shows in detail a half of the portions of the cell array corresponding to the I/O0.about.3. Disposed in these portions are memory cells, sense amplifiers and the like corresponding to the I/O0 and I/O1. In FIG. 11, the word lines extend longitudinally while the bit lines extend transversely. A cell array portion for one I/O is further divided into four cell array blocks. Disposed in the cell array blocks are memory cells arranged in rows and columns, sense amplifiers for these memory cells and so on.
In a small-capacity DRAM, column decoders are also disposed on the areas on which sense amplifiers in the cell array blocks are disposed. In a high density DRAM, however, it is common to adopt such an arrangement as shown in FIG. 12 in order to save chip area, disposing column decoders at an end of each of said four largely divided portions instead of in each cell array block and disposing column select lines, which are connected to the column decoder outputs, over the bit lines in parallel therewith, i.e., horizontally in FIG. 12, in second-level aluminum or the like so that each column select line is shared by the cell array blocks.
FIG. 10 shows in detail the inside of a cell array block and the connections of cell array blocks to each other. This arrangement adopts a shared sense amplifier scheme in which sense amplifiers SA0, SA1 . . . SA1022, SA1023 are disposed at the center of each cell array block. A bit-line connection selecting signal TG0 or TG1 causes the sense amplifiers SA0 . . . SA1023 to be selectively connected, through switch transistors 21, 22, 23, 24 . . . 141, 142, 143, 144 or 31, 32, 33, 34 . . . 151, 152, 153, 154, to bit line pairs BL0, /BL0, BL1, /BL1 . . . BL1022, /BL1022, BL1023, /BL1023 or BU0, /BU0, BU1, /BU1 . . . BU1022, /BU1022, BU1023, /BU1023. After the sense amplifiers start amplifying operations, column select lines CS0 . . . CS511 cause the sense amplifiers to be selectively connected, through column switch transistors 91, 92, 93, 94, to sub data buses D0A, /D0A, D0B, /D0B which extend in the word-line extending direction at the centers of the blocks.
For example, it is now supposed that a memory cell M0 is selected. In this case, the bit-line connection selecting signal TG0 becomes active, and the data read from the selected memory cell M0 to the bit line pair BL0, /BL0 by a word line WL0, is amplified by the sense amplifier SA0. Thereafter, the column select line CS0 becomes active and the sense amplifiers SA0 and SA1 are connected to the sub data buses D0A, /D0A and D0B, /D0B through the column switch transistors 91, 92 and 93, 94. Out of the sub data buses, the sub data buses D0A, /D0A connected to the memory cell M0 are selected by a block selecting switch BS0 and connected to I/O main data buses 7. Thereafter, the data is output from the data input/output terminal I/O0 through an output buffer 3 at the time of a read operation, and is entered from the data input/output terminal I/O0 through an input buffer 4 at the time of a write operation.
In such a conventional DRAM, the parasitic capacitance in the sub data buses becomes great, thus disadvantageously preventing the operation from being carried out at a high speed. For example, in the arrangement shown in FIG. 10 in which sub data buses in one cell array block are divided in two pairs, the number of the column switch transistors connected to one sub data bus, ends up reaching as many as 512. The drain junction capacitance and gate-drain capacitance of the column switch transistors form the parasitic capacitance of each sub data bus, thus increasing the sub data buses in parasitic capacitance. At the time of read operation, the sub data buses having large parasitic capacitance are required to be driven directly by the sense amplifiers. Accordingly, it takes much time to drive the sub data buses, thus disadvantageously preventing the operation to be conducted at a high speed. When the number of the sub data buses in one cell array block is increased, the number of the column switch transistors connected to one sub data bus is decreased to lower the sub data buses in parasitic capacitance. According to this method, however, the increase in the number of the sub data buses provokes an unallowable increase in chip area and an increase in power consumption. Thus, this method cannot serve as effective solving means.
In this connection, there is proposed a semiconductor memory disclosed by Japanese Laid-Open Patent Publication 1-241093. As shown in FIG. 13, this semiconductor memory is arranged in the following manner. In each of memory cell array blocks 200, 201 . . . , divided bit lines 220 . . . are respectively disposed for a large number of sense amplifiers 210 . . . and connected to a large number of common bit lines (sub data buses) 240 . . . through selection gate transistors 230 . . . . Before transferred to the common bit lines (sub data buses) 240, the output voltage of a selected memory cell array ( e.g., BL1, /BL1) is amplified by the sense amplifiers 210 on the divided bit lines 220. Then, the amplifying operation of the sense amplifiers 210 is stopped. By turning the selection gate transistors 230 . . . to ON, the divided bit lines 220 are connected to the common bit lines 240. Accordingly, the parasitic capacitance of the divided bit lines 220 . . . performs the function equivalent to that of the cell capacitance of a DRAM. With the selection gate transistors 230 . . . regarded as the transfer gates of DRAM cells, the electric charge is redistributed to a voltage which corresponds to the ratio in capacity between the divided bit lines 220 and the common bit lines 240. This compresses the voltage amplitude of the common bit lines (sub data buses), thus reducing the semiconductor memory in power consumption.
In the arrangement above-mentioned, however, after the sense amplifiers 210 . . . have fully amplified the voltage amplitudes of the divided bit lines 220 . . . , the voltages of the divided bit lines 220 . . . are transferred to the common bit lines. Accordingly, the read operation slows down and the timing control becomes complicated.
A conventional DRAM of the type above-mentioned presents the problem that it is difficult to develop it into a semiconductor memory with special functions being added, such as a video RAM. More specifically, in a video RAM, it is required to transfer the whole or a portion of data for one word line to a serial input/output register and to output the data serially at a high speed rate for a screen display. In a small-capacity DRAM comprising, in its entirety, one cell array block, the requirements above-mentioned are achieved by disposing one serial input/output register in all and by connecting the bit line pairs directly to the serial input/output register. However, in a high density DRAM comprising a large number of word lines, which are divided among a number of cell array blocks, it is required, in order to share one serial input/output register by the cell array blocks, that a large number of data transferring lines are disposed for connecting the sense amplifiers in the cell array blocks to the serial input/output register, the data transferring lines being in parallel with the bit lines. This means that, in the conventional arrangement, the data transferring lines run in parallel with a large number of column select lines. Such a wiring is difficult unless a wiring layer is added.
In this connection, the serial input/output register may be disposed, for example, for each of the cell array blocks. In such an arrangement, the bit line pairs may be connected directly to the serial input/output registers as conventionally done. This may solve the wiring problem, but disadvantageously increases the chip area to an unallowable extent owing to the increase in the number of the registers.